Imaging devices, including charge coupled devices (CCD) and complementary metal oxide semiconductor (CMOS) sensors have commonly been used in photo-imaging applications. A CMOS imager circuit includes a focal plane array of pixel cells, each one of the cells including a photosensor, for example, a photogate, photoconductor or a photodiode for accumulating photo-generated charge in the specified portion of the substrate. Each pixel cell has a charge storage region, formed on or in the substrate, which is connected to the gate of an output transistor that is part of a readout circuit. The charge storage region may be constructed as a floating diffusion region. In some imager circuits, each pixel may include at least one electronic device such as a transistor for transferring charge from the photosensor to the storage region and one device, also typically a transistor, for resetting the storage region to a predetermined charge level prior to charge transference.
In a CMOS imager, the active elements of a pixel cell perform the functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) resetting the storage region to a known state; (4) transfer of charge to the storage region; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing pixel charge. Photo charge may be amplified when it moves from the initial charge accumulation region to the storage region. The charge at the storage region is typically converted to a pixel output voltage by a source follower output transistor.
Exemplary CMOS imaging circuits, processing steps thereof, and detailed descriptions of the functions of various CMOS elements of an imaging circuit are described, for example, in U.S. Pat. No. 6,140,630; U.S. Pat. No. 6,376,868; U.S. Pat. No. 6,310,366; U.S. Pat. No. 6,326,652; U.S. Pat. No. 6,204,524; U.S. Pat. No. 6,333,205; and U.S. Pat. No. 6,852,591, all of which are assigned to Micron Technology, Inc. The disclosures of each of the forgoing are hereby incorporated by reference in their entirety.
A conventional imaging device 50, such as a CMOS imager, is illustrated in FIG. 1. The imaging device 50 has a conventional microlens 11 formed over a four transistor (4T) pixel cell 10. Light from a subject being imaged is incident as photons 1000 and passes through the conventional microlens 11, which is typically formed over a color filter 172. Each color filter allows predominantly light of a respective specific color to pass through to the photosensor 12 of the pixel cell 10. A color is defined to be light having a specific range of wavelengths. Typical color filters include red, green, and blue filters (RGB), or cyan, magenta, and yellow (CMY) filters.
The photosensor 12 has a p-type region 12a and an n-type region 12b in a p-type epitaxial layer 14, which may be formed over a p-type substrate. The pixel cell 10 includes the photosensor 12, which may be implemented as a pinned photodiode, transfer transistor gate 16, floating diffusion region 18, reset transistor gate 22, source follower transistor gate 24 with associated source/drain regions, and row select transistor gate 26 with associated source/drain regions. The photosensor 12 is electrically connected to the floating diffusion region 18 by the transfer transistor gate 16 when the transfer transistor gate 16 is activated by a transfer gate control signal TX.
The reset transistor gate 22 is connected between the floating diffusion region 18 and a pixel supply voltage (e.g., Vaa-Vpix) line 31. A reset control signal RST is used to activate the reset transistor gate 22, which resets the floating diffusion region 18 to the pixel supply voltage Vaa-Vpix level as is known in the art. The source follower transistor gate 24 is connected to the floating diffusion region 18 by a charge transfer line 23, and is connected between the array supply voltage line 31 and the row select transistor gate 26. The source follower transistor gate 24 responds to the charge stored at the floating diffusion region 18 to produce an electrical output voltage signal. The row select transistor gate 26 is controllable by a row select signal SEL for selectively connecting the source follower transistor gate 24 and its output voltage signal to a column line 28 of a pixel array.
Although the imaging device 50 of FIG. 1 works well, the size of the overall imaging device 50 is limited by the multitude of layers that are involved in the process of reading the photon-generated charge out of the pixel cell. As but one example, FIG. 1 includes a metallization layer M1 that may include the charge transfer line 23, which electrically couples the floating diffusion region 18 to the source follower transistor gate 24.
In addition, imaging device 50 also includes an additional metallization layer M2 that may include the column and voltage lines 28, 31. It should be noted that the specific conductors arranged in the M1 and M2 layer of a solid state imager may differ from those shown in FIG. 1, but typically at least two metallization layers M1, M2 are present. In more complex designs a third metallization layer M3 may also be employed above the M2 layer.
Because the plurality of interconnect lines in the M1 and M2 material layers (and M3 layer if employed) are fabricated from opaque, metal materials, the interconnect lines must be placed in positions in the array of pixels that do not interfere with the photons 1000 striking the photosensor 12. This requires a routing of the interconnect lines such that they do not cross the photosensors 12.
Additionally, the photons 1000 entering the imaging device 50 can reflect off of the opaque metal materials in M1 and M2 layers reducing the overall image capture by the photosensor 12, resulting in a poorer image quality. This too must be considered when routing conductors in the M1 and M2 layers.
Accordingly, an imager that facilitates conductive wiring without interfering with the light path to the photosensor 12 is desirable.